(a) Field of the Invention
The present invention relates to a semiconductor memory device having a monitoring pattern and, more particularly, to the arrangement of the monitoring patterns for monitoring the characteristics of memory cells and peripheral circuits in the semiconductor memory device.
(b) Description of the Related Art
Some conventional semiconductor memory devices have monitoring patterns for monitoring whether or not the transistors and interconnects formed on the product chip have desired characteristics. JP-A-56(1981)-83955, for example, proposes such a monitoring pattern in a semiconductor memory device. The monitoring pattern is generally disposed in the peripheral area or corner region of the product chip in view that there is scarcely any marginal area for the monitoring pattern in the central area or memory cell area of the memory device wherein a large number of transistors are integrated.
FIG. 1 is a partial top plan view of a conventional product chip of a memory device for showing an arrangement of the monitoring patterns. The monitoring patterns 13a, 13b and 13c are disposed in a space between bonding pads 12 and the corner region of the product chip 11.
FIG. 2 shows the detailed structure of one of the monitoring patterns in FIG. 1. The monitoring pattern shown therein has a specific pattern structure for monitoring the characteristics of a MOS transistor, and includes a pair of diffused regions 15, a gate electrode 14 made of polycrystalline silicon (polysilicon), and a plurality of through-holes 17 formed on the diffused region 15, which are similar to those in the memory cells. The monitoring pattern also includes pads 16 for deriving or inputting signals from and to the diffused regions 16 and the gate electrode 14.
The provision of the monitoring patterns in the product chip significantly increases the chip area for the product chip, because a large number of monitoring patterns should be provided for monitoring the characteristics of the semiconductor elements and interconnects in the product chip. For example, in a CMOS memory device, the monitoring patterns include at least two MOS monitoring patterns for monitoring nMOS and pMOS transistors, and threshold monitoring patterns for monitoring respective thresholds of transistors if there are a plurality of transistors having different thresholds. Separate monitoring patterns should be provided for the transistors in the memory cell. Moreover, other monitoring patterns should also be provided for monitoring characteristics of interconnects, such as electric resistance of polysilicon or refractive metals and through-holes, or withstand voltage or capacitance of the capacitor.
Among the proposals for suppressing the increase of the chip area accompanied by provision of the monitoring patterns, there is a proposal of "Test Element Group (TEG) Chip", wherein a large number of monitoring patterns are integrated in a single chip dedicated for monitoring ("Nikkei Micro-device", May 1995, pp. 56-58). FIG. 3 shows the proposed semiconductor wafer having TEG chips, wherein a large number of product chips 11 and a plurality of TEG chips 23 for monitoring the product chips 11 are arranged on the single wafer 21. By this proposal, the problem increase of the chip area does not arise; however, there arise other problems of complicated exposure steps for different chips, which causes reduction in the throughput of the fabrication of wafers, and a reduced yield of the chips from a single wafer.
There is another proposal in the above-mentioned publication, wherein monitoring patterns are provided on the scribe areas of the semiconductor wafer. FIG. 4 shows a partial top plan view of the proposed semiconductor wafer, wherein a plurality of monitoring patterns 13 are arranged along a stripe scribe areas 24 disposed for dicing the wafer into a plurality of product chips 11 after the completion of the monitoring. The proposed wafer solves the problem increase in the chip area of the product chips. The proposed wafer also solves the problem complicated exposure steps because the monitoring patterns 13 can be exposed concurrently with the exposure for the product chips 11. In view of these advantages, the proposed wafer is increasingly employed in the current fabrication process for the semiconductor memory device.
The proposed wafer, however, raises other problems in that dust of conductive materials is generated to degrade the yield of the product chips when a new fabrication technique is employed for the semiconductor memory devices, as detailed below.
First, the problem dust arises when a chemical-mechanical polishing (CMP) technique, such as described in "Semiconductor World", pp.99-101, Feb. 1995, is employed for planarization of the semiconductor chip. The CMP technique generally tends to expose the interconnect layers in the monitoring patterns formed on the scribe area, and raises the problem dust due to the peel-off of the conductive materials. This problem occurs especially in the structure of the DRAM, as shown in FIG. 5, wherein the memory cell area is higher than the peripheral area.
In FIG. 5, a memory cell in the memory cell area 22 includes a memory cell transistor having a pair of diffused regions 15a and 15b, or 15b and 15c, and a gate electrode 14a, or 14b, and a storage capacitor overlying the memory cell transistor and having a bottom electrode 31 and a top electrode 32. The peripheral area 20 includes a transistor having a pair of diffused regions 15d and 15e and a gate electrode 14c, which are similar to those in the memory cell area. Both the transistors in the memory cell area 22 and the peripheral area 20 have a substantially equal structure, and accordingly, the level of the memory cell area 22 is higher than the level of the peripheral area 20 because of the presence of the capacitor. In a typical 64 Mega-bit DRAM, the top electrode 32 of the storage capacitor has a thickness of 1500 to 2500 angstroms and the bottom electrode 31 has a thickness of 5000 to 8000 angstroms, which causes the difference of the level around 1 .mu.m between the memory cell area 22 and the peripheral area 20. In this configuration, it is difficult to completely planarize an insulation film 33 in both the areas 22 and 20 by the CMP technique, and accordingly, the resultant geometry depends on the levels of the underlying layers in both the areas 22 and 20.
Some of the monitoring patterns disposed in the scribe area for monitoring the characteristics of the memory cells have a level equal to the level of the memory cell. Accordingly, in the vicinity of the scribe area, monitoring patterns having a smaller space and a higher level than the peripheral area exist adjacent to the peripheral area having a larger space and a lower level. This raises difficulty in the CMP technique, and the resultant geometry of the monitoring patterns after the CMP process is generally based on the level of the peripheral area, resulting in a lower level of the monitoring patterns.
FIG. 6 schematically shows the geometry of the typical DRAM before and after the CMP process. In the drawing, the memory cells and the monitoring pattern each including transistors and a capacitor are shown by hatched boxes 10 and 18. As understood from the drawing, the top insulator film 33 after the deposition thereof has a smaller thickness in the monitoring pattern 10 compared to the memory cells 18 due to the lower level of the peripheral area. That is, the thickness of the top insulator layer 33 is generally uniform in the peripheral area and in the scribe area. Accordingly, after the CMP process, as shown by a chain line, the top electrode of the monitoring pattern tends to be exposed, which causes dust of the conductive materials to be scattered on the wafer, thereby degrading the characteristics of the memory device and thus the yield thereof.
Second, the problem dust arises in a step for removing a polyimide film if a large scale chip such as for a DRAM is fabricated by a lead on chip (LOC) technique, which is described in "Nikkei Micro-device", Feb. 1992, pp 77-84. The LOC process can save a conventional die pad for supporting the product chip by arranging an inner lead on the product chip (i.e., lead on chip), the inner lead having a function for supporting and fixing the product chip as well as an ordinary function for transmitting input/output signals to and from the chip.
FIG. 7 shows the product chip fabricated by the LOC technique before dicing of the wafer. An inner lead 36 is bonded to the product chip for supporting the product chip with an intervention of an adhesive tape 37 and a polyimide film 38 therebetween. The polyimide film 38 functions for alleviating the stress applied to the product chip from the adhesive tape 37. A passivation film 39 covers the surface of the entire product chip except for the scribe area 24. In this configuration, the polyimide film 38 as well as the passivation film 39 has been removed from the scribe area 24 in view that the polyimide film 38 and the passivation film 39 may obstruct the dicing of the wafer. In the polyimide removing step, the monitoring pattern may also be exposed in the scribe area 24. Especially, if combined with the CMP process, the polyimide removing step exposes the top electrode of the monitoring pattern, which causes the problem dust of the conductive materials.